1. Field of the Invention
The present invention relates to a display apparatus and particularly to a TFT gate driving apparatus for driving a pixel array on a panel.
2. Description of the Prior Art
FIG. 1 shows a conventional TFT gate driving circuit, which is built into a driver chip 11 and includes pairs of a NMOS and PMOS transistor 111 and 112. In each pair, the drains of the NMOS transistors 111 and PMOS transistor 112 are commonly coupled to a scan line 121 of a pixel array 122 on a panel 12, the sources of the NMOS transistor 111 and PMOS transistor 112 are respectively coupled to receive voltages VGH and VGL, and the gates of the NMOS transistor 111 and PMOS transistor 112 are commonly coupled to a gate driving signal GDS. The NMOS transistor 111 and PMOS transistor 112 are high-voltage devices.
When a high logic level is asserted in the gate driving signal GDS, the NMOS transistor 111 is turned on and the PMOS transistor 112 is turned off, which results in the voltage VGL applied to the scan line 121. Conversely, when a low logic level is asserted in the gate driving signal GDS, the NMOS transistor 111 is turned off and the PMOS transistor 112 is turned on, resulting in the voltage VGH applied to the scan line 121.
Those skilled in the art will appreciate that high-voltage devices occupy a large circuit area. The conventional driving circuit includes a large number of high-voltage devices 111 and 112, which is disadvantageous to size-reduction of the driver chip 11.